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BT0068 Computer Organization and Architecture Paper-1

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  1. Convert the following decimal numbers to binary:


      a. 1231
=1,0,0,1,1,0,0,1,1,1,1
      b. 673
=1,0,1,0,1,0,0,0,0,1  

c.1998
=1,1,1,1,1,0,0,1,1,1,0

  1. Give and explain one stage of logic circuit.


In many computers only four: AND, OR, XOR (exclusive OR) and complement

micro-operations are implemented. Other 12 micro- operations can be derived from these

four micro-operations. Figure 8 shows one bit, that is the ih bit stage of the four logic

operations. Please note that the circuit consist of 4 gates and a 4 x 1 MUX. The ih bits of

Register R1 and Rz are passed through the circuit. On the basis of selection inputs Soand S1

the desired micro-operation is oblained.


  1. Explain Von Neumann Architecture.

von Neumann Architecture. John von Neumann elucidated the first practical stored-program computer architecture (scheme for connecting computer components) in the mid-1940s. It is comprised of the five classical components (input, output, processor, memory, and datapath). The processor is divided into an arithmetic logic unit (ALU) and control unit, a method of organization that persists to the present. Within the processor, the ALU datapath mediates data transfer for computation. The registers are fast memory modules from/to which data can be read/written to support streaming computation, as shown in Figure 1.8. Within the ALU, an accumulator supports efficient addition or incrementation of values corresponding to variables such as loop indices.
 


Figure 1.8. Schematic diagram of von Neumann architecture, adapted from [Maf01].
The von Neumann architecture has a significant disadvantage - its speed is dependent on the bandiwdht or throughput of the datapath between the processor and memory. This is called the von Neumann bottleneck.
A von Neumann architecture computer performs or emulates the following sequence of steps:
  1. Fetch the next instruction from memory at the address in the program counter.
  2. Add the length of the instruction to the program counter.
  3. Decode the instruction using the control unit. The control unit commands the rest of the computer to perform some operation. The instruction may change the address in the program counter, permitting repetitive operations. The instruction may also change the program counter only if some arithmetic condition is true, giving the effect of a decision, which can be calculated to any degree of complexity by the preceding arithmetic and logic.
  4. Go back to step 1.


  1. Compare the register organizations of 8085, Z8000 and MC68000.

The 8085 Architecture follows the "von Neumann architecture", with a 16-bit address bus, and a 8-bit data bus.The 8085 used a multiplexed Data Bus i.e.the address was split between the 8-bit address bus and 8-bit data bus. (For saving Number of Pins)

Registers:

The 8085 can access 216 (= 65,536) individual 8-bit memory locations, or in other words, its address space is 64 KB. Unlike some other microprocessors of its era, it has a separate address space for up to 28 (=256) I/O ports. It also has a built in register array which are usually labeled A (Accumulator), B, C, D, E, H, and L. Further special-purpose registers are the 16-bit Program Counter (PC), Stack Pointer (SP), and 8-bit flag register F. The microprocessor has three maskable interrupts (RST 7.5, RST 6.5 and RST 5.5), one Non-Maskable interrupt (TRAP), and one externally serviced interrupt (INTR). The RST n.5 interrupts refer to actual pins on the processor-a feature which permitted simple systems to avoid the cost of a separate interrupt controller chip.

Buses

* Address bus - 16 line bus accessing 216 memory locations (64 KB) of memory.
* Data bus - 8 line bus accessing one (8-bit) byte of data in one operation. Data bus width is the traditional measure of processor bit designations, as opposed to address bus width, resulting in the 8-bit microprocessor designation.
* Control buses - Carries the essential signals for various operations.

The Z8000 is a 16-bit microprocessor introduced by Zilog in 1979The register set consisted of sixteen 16-bit registers, and there were instructions that could use them as 8-bit, 16-bit, 32-bit, and 64-bit registers. The register set was completely orthogonal, with register 15 conventionally designated as stack pointer, and register 14 for stack segment.
There was both a user mode and a supervisor mode.
Like the Z80, the Z8000 included built-in DRAM refresh circuitry. Although an attractive feature for designers of the time, overall the Z8000 was not especially fast and had some bugs, and in the end it was overshadowed by the x86 family.
The most significant of the 32-bit designs is the MC68000, introduced in 1979. The 68K, as it was widely known, had 32-bit registers but used 16-bit internal data paths and a 16-bit external data bus to reduce pin count, and supported only 24-bit addresses. Motorola generally described it as a 16-bit processor, though it clearly has 32-bit architecture. The combination of high performance, large (16 megabytes or 224 bytes) memory space and fairly low cost made it the most popular CPU design of its class.

  1. Give the advantages and disadvantages of physical and functional buses.

In computer architecture, a bus is a subsystem that transfers data between computer components inside a computer or between computers.
in a network, the master scheduler controls the data traffic. If data is to be transferred, the requesting computer sends a message to the scheduler, which puts the request into a queue. The message contains an identification code which is broadcast to all nodes of the network. The scheduler works out priorities and notifies the receiver as soon as the bus is available.
The identified node takes the message and performs the data transfer between the two computers. Having completed the data transfer the bus becomes free for the next request in the scheduler's queue.Advantage: Any computer can be accessed directly and messages can be sent in a relatively simple and fast way. Disadvantage: A scheduler is required to organize the traffic by assigning frequencies and priorities to each signal.
Functional dedication- a bus has a specific funtion.exqmple: Three buses identifies for carrying address,data and control signal s.They are Address Bus,Data Bus, and Control Bus.
Physical dedication-use of multiple buses,each of which connect only a subset of compnents using the bus ,Advantage of Physical Bus -it offer throughput because there is less bus connection
Disadvantage -increased size and cost of the system.
These are also referred  to as non-dedicted .Same bus may be used for various function.

  1. Explain different types of binary codes.

The binary numeral system, or base-2 number system, represents numeric values using two symbols, 0 and 1. More specifically, the usual base-2 system is a positional notation with a radix of 2. Owing to its straightforward implementation in digital electronic circuitry using logic gates, the binary system is used internally by all modern computers.
Counting in binary is similar to counting in any other number system. Beginning with a single digit, counting proceeds through each symbol, in increasing order. Decimal counting uses the symbols 0 through 9, while binary only uses the symbols 0 and 1
      1. Hexadecimal

Binary may be converted to and from hexadecimal somewhat more easily. This is because the radix of the hexadecimal system (16) is a power of the radix of the binary system (2). More specifically, 16 = 24, so it takes four digits of binary to represent one digit of hexadecimal
      1. Octal

Binary is also easily converted to the octal numeral system, since octal uses a radix of 8, which is a power of two (namely, 23, so it takes exactly three binary digits to represent an octal digit). The correspondence between octal and binary numerals is the same as for the first eight digits of hexadecimal in the table above. Binary 000 is equivalent to the octal digit 0, binary 111 is equivalent to octal 7, and so forth.
The reflected binary code, also known as Gray code after Frank Gray, is a binary numeral system where two successive values differ in only one bit.The problem with natural binary codes is that, with real (mechanical) switches, it is very unlikely that switches will change states exactly in synchrony. In the transition between the two states shown above, all three switches change state. In the brief period while all are changing, the switches will read some spurious position. Even without keybounce, the transition might look like 011 — 001 — 101 — 100. When the switches appear to be in position 001, the observer cannot tell if that is the "real" position 001, or a transitional state between two other positions. If the output feeds into a sequential system (possibly via combinational logic) then the sequential system may store a false value.

7. Give and explain the block diagram of the bus system with four registers.
Busses are collections of wires used to carry signals around the computer. They are commonly printed as parallel tracks on circuit boards. Slots are sockets that enable cards to be connected to the system bus. An 8-bit computer typically has registers 8 bits wide and 8 wires in a bus. A 16-bit computer has 16 bit registers and 16 address and data wires and so on. The original IBM PC had 8 data wires and 20 address wires enabling one megabyte of RAM to be accessed. 32 bit registers and busses are now usual (1997-2003).
  The CPU has four general-purpose registers called AL, BL, CL and DL. These are eight bits or one byte wide. Registers can hold unsigned numbers in the range 0 to +255 and signed numbers in the range –128 to +127. These are used as temporary storage locations. Registers are used in preference to RAM locations because it takes a relatively long time to transfer data between RAM and the CPU. Faster computers generally have more CPU registers or memory on the CPU chip.
The registers are named AL, BL, CL and DL because the 16-bit version of this CPU has more registers called AH, BH, CH and DH. The 'L' means Low and the 'H' means High. These are the low and high ends of the 16-bit register.
      1. Special Purpose Registers

The special purpose registers in the CPU are called IP, SR and SP.
        1. IP is the Instruction pointer

This register contains the address of the instruction being executed. When execution is complete, IP is increased to point to the next instruction. Jump instructions alter the value of IP so the program flow jumps to a new position. CALL and INT also change the value stored in IP. In the RAM displays, the instruction pointer is highlighted red with yellow text.
        1. SR is the Status Register

This register contains flags that report the CPU status.
The 'Z' zero flag is set to one if a calculation gave a zero result.
The 'S' sign flag is set to one if a calculation gave a negative result.
The 'O' overflow flag is set if a result was too big to fit in a register.
The 'I' interrupt is set if interrupts are enabled. See CLI and STI.
        1. SP is the Stack Pointer

The stack is an area of memory organised using the LIFO last in first out rule. The stack pointer points to the next free stack location. The simulator stack starts at address BF just below the RAM used for the video display. The stack grows towards address zero. Data is pushed onto the stack to save it for later use. Data is popped off the stack when needed. The stack pointer SP keeps track of where to push or pop data items. In the RAM displays, the stack pointer is highlighted blue with yellow text.
      1. Random Access Memory

The simulator has 256 bytes of ram. The addresses are from 0 to 255 in decimal numbers or from [00] to [FF] in hexadecimal. RAM addresses are usually given in square brackets such as [7C] where 7C is a hexadecimal number. Read [7C] as "the data stored at location 7C".
        1. Data Bus

The Data Bus is used to carry data between the CPU, RAM and IO ports. The simulator has an 8-bit data bus.
        1. Address Bus

The Address Bus is used to specify what RAM address or IO port should be used. The simulator has an 8-bit address bus.
        1. Control Bus

The Control Bus This has a wire to determine whether to access RAM or IO ports. It also has a wire to determine whether data is being read or written. The CPU reads data when it flows into the CPU. It writes data when it flows out of the CPU to RAM or the IO ports.
The System Clock wire carries regular pulses so that all the electronic components can function at the correct times. Clock speeds between 100 and 200 million cycles per second are typical (1997). This is referred to as the clock speed in MHz or megahertz. The simulator runs in slow motion at about one instruction per second. This is adjustable over a small range.
        1. Hardware Interrupts

Hardware Interrupts require at least one wire. These enable the CPU to respond to events triggered by hardware such as printers running out of paper. The CPU processes some machine code in response to the interrupt. When finished, it continues with its original task. The IBM PC has 16 interrupts controlled by 4 wires.



8. Explain the System Bus structure.
In computer architecture, a bus is a subsystem that transfers data between computer components inside a computer or between computers.
Early computer buses were literally parallel electrical buses with multiple connections, but the term is now used for any physical arrangement that provides the same logical functionality as a parallel electrical bus. Modern computer buses can use both parallel and bit-serial connections, and can be wired in either a multidrop (electrical parallel) or daisy chain topology, or connected by switched hubs, as in the case of USB.At one time, "bus" meant an electrically parallel system, with electrical conductors similar or identical to the pins on the CPU. This is no longer the case, and modern systems are blurring the lines between buses and networks.















Figure 5.1 is a simplified view of a CPU, indicating its connection to the rest of the system via the system bus. You will recall (Lecture 1) that the major components of the CPU are an arithmetic and logic unit (ALU) and a control unit (CU). The ALU does the actual computation or processing of data. The con trol unit controls the movement of data and instructions into and out of the CPU and controls the operation of the ALU. In addition, the figure shows a minimal internal memory, consisting of a set of storage locations, called registers.

9.Explain the register organization of 8086.
The 8086 had eight (more or less general) 16-bit registers including the stack pointer, but excluding the instruction pointer, flag register and segment registers. Four of them, AX, BX, CX, DX, could also be accessed as twice as many 8-bit registers (see figure) while the other four, BP, SI, DI, SP, were 16-bit only.
Due to a compact encoding inspired by 8-bit processors, most instructions were one-address or two-address operations which means that the result were stored in one of the operands. At most one of the operands could be in memory, but this memory operand could also be the destination, while the other operand, the source, could be either register or immediate. A single memory location could also often be used as both source and destination which, among other factors, further contributed to a code density comparable to (often better than) most eight bit machines.
Although the degree of generality of most registers were much greater than in the 8080 or 8085, it was still fairly low compared to the typical contemporary minicomputer, and registers were also sometimes used implicitly by instructions. While perfectly sensible for the assembly programmer, this complicated register allocation for compilers compared to more regular 16- and 32-bit processors such as the PDP-11, VAX, 68000, etc.; on the other hand, compared to semi-contemporary simple (but popular and ubiquitous) 8-bit microprocessors such as the 6502, 6809, or 8085, it was significantly easier to generate code for the 8086 design.
The 8086 also featured 64 KB of 8-bit (or alternatively 32 K-word of 16-bit) I/O space. A 64 KB (one segment) stack growing towards lower addresses is supported by hardware; 2-byte words are pushed to the stack and the stack top (bottom) is pointed out by SS:SP. There are 256 interrupts, which can be invoked by both hardware and software. The interrupts can cascade, using the stack to store the return addresses.
The processor had some new instructions (not present in the 8080 and 8085) to better support stack based high level programming languages such as Pascal and PL/M; some of the more useful ones were push mem-op, and ret size, supporting the "pascal calling convention" directly. (Several others, such as push immed and enter, would be added in the subsequent 80186, 80286, and 80386 designs.) It also had a stack-marker mechanism.

  1. Explain the single bus structure.

In this type of connection,three units share a single bus.Hence the information can be transfered only between two units at atime.Here the I/O units use the same memory address space.This simplifies programming of I/O units as no special I/O instruction are needed.THis is one of advantages of single bus organization.The transfer of information over a bus cannot be done at a speed comparable to the operating speed of all the devices connected to the bus.Bus architecture uses common data signaling paths for multiple devices, rather than have separate connections between each set of devices that need to communicate. For example, a data bus can be used for data to and from dynamic RAM, to and from mass storage, and to and from peripheral devices, rather than having one set of wires from the CPU for memory, another set for I/O, and so forth. There is often a mechanism for devices to signal when they need to use the bus, while it is in use, and what is the nature of the use (data/instructions/controls/etc). Bus control can become quite complicated when numerous asynchronous processes are attempting to share the bus efficiently.




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